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Johns Hopkins University | EN.520.644

Fpga Synthesis Lab

3.0

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An advanced laboratory course in the application of FPGA technology to information processing, using VHDL synthesis methods for hardware development. The student will use commercial CAD software for VHDL simulation and synthesis, and implement their systems in programmable XILINX 20,000 gate FPGA devices. The lab will consist of a series of digital projects demonstrating VHDL design and synthesis methodology, building up to final projects at least the size of an 8-bit RISC computer. Projects will encompass such things as system clocking, flip-flop registers, state-machine control, and arithmetic. The students will learn VHDL methods as they proceed through the lab projects, and prior experience with VHDL is not a prerequisite.

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Lecture Sections

(01)

No location info
P. Pouliquen
16:30 - 18:50

(02)

No location info
P. Pouliquen
16:30 - 18:50