3.0

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This course offers a comprehensive introduction to the design of application-specific integrated circuits (ASICs) using modern VLSI CAD tools. Students will learn the complete ASIC design flow-from RTL design in hardware description languages (HDL) to layout and design rule checking-using industry-standard tools such as Cadence. Students need to know Verilog and Digital Hardware Design as prerequisites for this course. Through hands-on labs and projects, students will explore tradeoffs and challenges in designing large-scale chips, including performance, power efficiency, testability, and manufacturability. Key topics include: •RTL synthesis using standard cell libraries •Static timing analysis •Design for test and fault simulation •Physical design: floorplanning, placement, routing, and clock tree synthesis •Design rule checking and final GDSII generation Learning Objectives: •Understand the ASIC implementation flow and associated design challenges •Apply industry practices to optimize for power, performance, and area •Incorporate test structures and validate design correctness •Gain practical experience with CAD tools used in semiconductor industry